TechVare Learning

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170+ expert-led courses across ARM, VLSI, Embedded, Cloud, and AI domains. All taught by industry veterans with 10-25+ years of experience.

170+
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40+
Expert Instructors
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Technology Domains
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10 Courses Found

Filtered by: VLSI Design

DFT & ATPG Essentials
VLSIAdvanced

DFT & ATPG Essentials

Learn Design-for-Test techniques, scan insertion, ATPG, BIST, and manufacturing test strategies.

⏱️ 55 hours
👨‍🏫 Srini Reddy
Formal Verification Advanced
VLSIAdvanced

Formal Verification Advanced

Master formal verification techniques for proving design correctness and finding corner-case bugs.

⏱️ 60 hours
👨‍🏫 Dr. Mahesh Kumar
Low Power VLSI Design
VLSIAdvanced

Low Power VLSI Design

Master low-power design techniques using UPF/CPF, multi-voltage domains, and power optimization.

⏱️ 60 hours
👨‍🏫 Dr. Padma Shree
Physical Design End-to-End
VLSIAdvanced

Physical Design End-to-End

Complete physical design flow from floorplanning to GDSII signoff using industry-standard tools.

⏱️ 70 hours
👨‍🏫 Dr. Lakshmi Prasad
RISC-V Architecture & SoC Design
VLSIIntermediate

RISC-V Architecture & SoC Design

Design RISC-V based SoCs with custom instructions, verification, and system integration.

⏱️ 55 hours
👨‍🏫 Ashok Patel
RTL Design Fundamentals
VLSIBasic

RTL Design Fundamentals

Master RTL design principles, Verilog coding, and digital design best practices for ASIC/FPGA.

⏱️ 50 hours
👨‍🏫 Dr. Mohan Rao
Static Timing Analysis Mastery
VLSIAdvanced

Static Timing Analysis Mastery

Master STA concepts, PrimeTime/Tempus tools, and timing closure techniques for complex designs.

⏱️ 60 hours
👨‍🏫 Arun Kumar
Synthesis & Optimization Techniques
VLSIAdvanced

Synthesis & Optimization Techniques

Master synthesis tools (Design Compiler, Genus) and advanced optimization for area, timing, and power.

⏱️ 55 hours
👨‍🏫 Vivek Sharma
SystemVerilog for Design & Verification
VLSIIntermediate

SystemVerilog for Design & Verification

Master SystemVerilog for both RTL design and advanced verification testbench development.

⏱️ 55 hours
👨‍🏫 Rajiv Menon
UVM Methodology Complete
VLSIAdvanced

UVM Methodology Complete

Become UVM expert with comprehensive training from basics to advanced testbench development.

⏱️ 70 hours
👨‍🏫 Venkat Krishnan

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